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| preliminary cy14b116k/cy14b116m 16-mbit (2048 k 8/1024 k 16) nvsram with real time clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-67786 rev. *i revised november 5, 2014 features 16-mbit nonvolatile static random access memory (nvsram) ? 25-ns and 45-ns access times ? internally organized as 2048 k 8 (cy14b116k), 1024 k 16 (cy14b116m) ? hands-off automatic store on power-down with only a small capacitor ? store to quantumtrap nonvolatile elements is initiated by software, device pin, or autostore on power-down ? recall to sram initiated by software or power-up high reliability ? infinite read, write, and recall cycles ? 1 million store cycles to quantumtrap ? data retention: 20 years sleep mode operation full-featured real time clock (rtc) ? watchdog timer ? clock alarm with programmable interrupts ? backup power fail indication ? square wave output with programmable frequency (1 hz, 512 hz, 4096 hz, 32.768 khz) ? capacitor or battery backup for rtc ? backup current of 0.45 ? a (typical) low power consumption ? active current of 75 ma at 45 ns ? standby mode current of 750 ? a ? sleep mode current of 10 ? a operating voltage: v cc = 2.7 v to 3.6 v industrial temperature: ?40 ? c to +85 ? c packages ? 44-pin thin small-outline package (tsop ii) ? 54-pin thin small-outline package (tsop ii) ? 165-ball fine-pitch ball grid array (fbga) package restriction of hazardous substances (rohs) compliant functional description the cypress cy14b116k/cy14b116m combines a 16-mbit nvsram with a full-featured rtc in a monolithic integrated circuit. the nvsram is a fast sram with a nonvolatile element in each memory cell. the memory is organized as 2048 k bytes of 8 bits each or 1024 k words of 16 bits each. the embedded nonvolatile elements incorporate the quantumtrap technology, producing the world?s most reliable nonvolatile memory. the sram can be read and written an infinite number of times. the nonvolatile data residing in the nonvolatile elements do not change when data is written to the sram. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at po wer-down. on po wer-up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. the rtc function provides an accurate clock with leap year tracking and a programmable, high-accuracy oscillator. the alarm function is programmable for periodic minutes, hours, days, or months alarms. there is also a programmable watchdog timer. for a complete list of related documentation, click here .
preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 2 of 42 control logic ce we oe software detect hsb zz sleep mode control power control store / recall control static ram array 4096 x 4096 quantumtrap 4096 x 4096 store recall column io column decoder sense amps input buffers row decoder dq - v rtccap v rtcbat v cap v cc x in x out int rtc mux output buffers zz ble bhe 0 dq 15 a - 0 a 20 a - 2 a 14 a - 0 a 11 a - 12 a 20 logic block diagram [1, 2, 3] [4] notes 1. address a 0 ?a 20 for 8 configuration and address a 0 ?a 19 for 16 configuration. 2. data dq 0 ?dq 7 for 8 configuration and data dq 0 ?dq 15 for 16 configuration. 3. ble , bhe are applicable for x16 configuration. 4. tsop ii package is offered in single ce and bga package is offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 3 of 42 contents pinouts .............................................................................. 4 device operation .............................................................. 6 sram read ....................................................................... 6 sram write ....................................................................... 6 autostore operation (power-down) ............................... 6 hardware store (hsb) operation................................. 7 hardware recall (power-up) ....................................... 7 software store ............................................................... 7 software recall............................................................. 7 sleep mode........................................................................ 8 preventing autostore....................................................... 9 data protection ............................................................... 10 real time clock operation............................................ 10 nvtime operation...................................................... 10 clock operations....................................................... 10 reading the clock ..................................................... 10 setting the clock ....................................................... 10 backup power ........................................................... 10 stopping and starting the osc illator............ .............. 11 calibrating the clock ................................................. 11 alarm ......................................................................... 11 watchdog timer ........ .............. .............. .............. ...... 12 programmable square wave generator................... 12 power monitor ........................................................... 12 backup power monitor .............................................. 13 interrupts ................................................................... 13 flags register ........................................................... 14 rtc external components ....................................... 15 pcb design considerations for rtc............................ 15 layout requirements ................................................ 15 maximum ratings........................................................... 22 operating range............................................................. 22 dc electrical characteristics ........................................ 22 data retention and endurance ..................................... 23 capacitance .................................................................... 23 thermal resistance........................................................ 23 ac test conditions ........................................................ 24 rtc characteristics ....................................................... 24 ac switching characteristics ....................................... 25 autostore/power-up recall characteristics............ 29 sleep mode characteristics........................................... 30 software controlled store and recall characteristics................................................................ 31 hardware store characteristics................................. 32 for 16 configuration ............................................... 33 truth table for sram operations................................ 33 for 8 configuration ................................................. 33 for 16 configuration ............................................... 34 ordering information...................................................... 35 package diagrams.......................................................... 36 acronyms ........................................................................ 39 document conventions ................................................. 39 units of measure ....................................................... 39 errata ............................................................................... 40 part numbers affected .............................................. 40 16-mbit (2048 k 8, 1024 k 16) nvsram qualification status ................................................... 40 16-mbit (2048 k 8, 1024 k 16) nvsram errata summary ........................................................ 40 document history page ................................................. 42 sales, solutions, and legal information ...................... 44 worldwide sales and design supp ort............. .......... 44 products .................................................................... 44 psoc? solutions ...................................................... 44 cypress developer community................................. 44 technical support .................. ................................... 44 preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 4 of 42 pinouts figure 1. pin diagram: 44-pin tsop ii ( 8) figure 2. pin diagram: 54-pin tsop ii ( 16) figure 3. pin diagram: 165-ball fbga (16) 1 2 3 4 5 6 7 8 9 10 11 a nc a 6 a 8 we ble ce 1 nc oe a 5 a 3 nc b nc dq 0 dq 1 a 4 bhe ce 2 nc a 2 nc nc nc c zz nc nc v ss a 0 a 7 a 1 v ss nc dq 15 dq 14 d nc dq 2 nc v ss v ss v ss v ss v ss x in nc nc e nc v cap nc v cc v ss v ss v ss v cc x out dq 13 nc f nc dq 3 nc v cc v cc v ss v cc v cc nc nc dq 12 g hsb nc nc v cc v cc v ss v cc v cc nc nc nc h nc nc v cc v cc v cc v ss v cc v cc v cc nc nc j nc nc nc v cc v cc v ss v cc v cc nc dq 8 nc k nc nc dq 4 v cc v cc v ss v cc v cc nc nc nc l nc dq 5 nc v cc v ss v ss v ss v cc nc nc dq 9 m nc nc nc v ss v ss v ss v ss v ss nc dq 10 nc n int dq 6 dq 7 v ss a 11 a 10 a 9 v ss nc nc nc p nc nc nc a 13 a 19 v rtcbat a 18 a 12 nc dq 11 nc r nc nc a 15 nc a 17 v rtccap a 16 nc [5] a 14 nc nc nc a 8 xin xout v ss dq 6 dq 5 dq 4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 oe a 9 ce a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 a 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) a 10 v rtcbat we dq 7 hsb int v ss v cc v cap v rtccap (x8) a 17 a 18 a 20 [5] dq 7 dq 6 dq 5 dq 4 v cc dq 3 dq 2 dq 1 dq 0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 oe ce v cc int v ss a 9 nc a 18 54 53 52 51 49 50 hsb bhe ble dq 15 dq 14 dq 13 dq 12 v ss dq 11 dq 10 dq 9 dq 8 (x16) v rtccap v rtcbat xin xout a 16 a 17 a 19 top view (not to scale) 54 - tsop ii note 5. address expansion for the 32-mbit. nc pin not connected to die. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 5 of 42 table 1. pin definitions pin name i/o type description a 0 ?a 20 input address inputs. used to select one of the 2,097,15 2 bytes of the nvsram fo r the 8 configuration. a 0 ?a 19 address inputs. used to select one of the 1,048,57 6 words of the nvsram fo r the 16 configuration. dq 0 ?dq 7 input/output bidirectional data i/o lines for the 8 configuration . used as input or output lines depending on operation. dq 0 ?dq 15 bidirectional data i/o lines for the 16 configuration . used as input or output lines depending on operation. we input write enable input, active low . when selected low, data on the i/o pins is written to the specific address location. ce input chip enable input in tsop ii package, active low . when low, selects the chip. when high, deselects the chip. ce 1, ce 2 chip enable input in fbga package. the device is selected and a memory access begins on the falling edge of ce 1 (while ce 2 is high) or the rising edge of ce 2 (while ce 1 is low). oe input output enable, active low. the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. ble input byte enable, active low . when selected low, enables dq 7 ?dq 0 . bhe input byte enable, active low . when selected low, enables dq 15 ?dq 8 . zz [6] input sleep mode enable. when the zz pin is pulled low, the device enters a low-power sleep mode and consumes the lowest power. since th is input is logically and?ed with ce , zz must be high for normal operation. x out [7] output crystal connection . drives crystal on start-up. x in [7] input crystal connection. for 32.768-khz crystal. v rtccap [7] power supply capacitor supplied backup rtc supply voltage . left unconnected if v rtcbat is used. v rtcbat [7] power supply battery supplied backup rtc supply voltage . left unconnected if v rtccap is used. int [ 7 ] output interrupt output/cal ibration/square wave . programmable to respond to the clock alarm, the watchdog timer, and the power monitor. in addition, programmabl e to be either active high (push or pull) or low (open drain). in the calibration mode, a 512-hz squar e wave is driven out. in the square wave mode, you can select a frequency of 1 hz, 512 hz, 4,096 hz , or 32,768 hz to be used as a continuous output. v cc power supply power supply inputs to the device . v ss power supply ground for the device . must be connected to ground of the system. hsb input/output hardware store busy (hsb ) .when low, this output indicates that a hardware store is in progress. when pulled low external to the chip, it initiates a nonvolatile store operation. after each hardware and software store operation, hsb is driven high for a short time (t hhhd ) with standard output high current and then a weak internal pull-up resistor keep s this pin high (external pull-up resistor connection optional). v cap power supply autostore capacitor . supplies power to the nvsram during po wer loss to store data from sram to nonvolatile elements. nc nc no connect . die pads are not connected to the package pin. notes 6. sleep mode feature is offered only in the 165-ball fbga package. 7. left unconnected if rtc feature is not used. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 6 of 42 device operation the cy14b116k/cy14b116m nvsram is made up of two functional components paired in the same physical cell. these are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferr ed to the nonvolatile cell (the store operation) automatically at power-down, or from the nonvolatile cell to the sram (the recall operation) on power-up. both the store and recall operations are also available under software control. using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14b116k/cy14b116m supports infinite reads and writes to the sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 1 million store operations. see the truth table for sram operations on page 33 for a complete description of read and write modes. sram read the cy14b116k/cy14b116m performs a read cycle whenever ce and oe are low, and we , zz , and hsb are high. the address specified on pins a 0 ?a 20 or a 0 ?a 19 determines which of the 2,097,152 data bytes or 1,048,576 words of 16 bits each are accessed. byte enables (bhe , ble ) determine which bytes are enabled to the output, in the case of 16-bit words. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data output repeatedly responds to address changes within the t aa access time without the need for transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycl e. the data on the common i/o pins dq 0 ?dq 15 is written into the memory if it is valid t sd before the end of a we -controlled write or before the end of a ce -controlled write. the byte enable inputs (bhe , ble ) determine which bytes are written, in the case of 16-bit words. keep oe high during the entire write cycle to avoi d data bus contention on the common i/o lines. if oe is left low, the internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation (power-down) the cy14b116k/cy14b116m stores data to the nonvolatile quantumtrap cells using one of the three storag e operations. these three operations are: hardware store, activated by the hsb ; software store, activate d by an address sequence; autostore, on device power-down. the autostore operation is a unique feature of nvsram and is enabled by default on the cy14b116k/cy14b116m. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a store operation during power-down. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc and a store operation is initiated with power provided by the v cap capacitor. note if the capacitor is not connected to the v cap pin, autostore must be disabled using the soft sequence specified in the section preventing autostore on page 9 . if autostore is enabled without a capacitor on the v cap pin, the device attempts an autostore operation without sufficient char ge to complete the store. this corrupts the data stored in the nvsram. figure 4. autostore mode figure 4 shows the proper connection of the storage capacitor (v cap ) for the automatic stor e operation. refer to dc electrical characteristics on page 22 for the size of the v cap . the voltage on the v cap pin is driven to v vcap by a regulator on the chip. a pull-up resistor should be placed on we to hold it inactive during power-up. this pull-up resi stor is only effective if the we signal is in tristate during power-up. when the nvsram comes out of power-up-recall, the ho st microcontroller must be active or the we held inactive until the host microcontroller comes out of reset. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place (which sets a write latch) since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. 0.1 uf v cc v cap we v cap v ss v cc 10 k : preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 7 of 42 hardware store (hsb ) operation the cy14b116k/cy14b116m provides the hsb pin to control and acknowledge the store operations. the hsb pin is used to request a hardware store cycle. when the hsb pin is driven low, the device conditionally initiates a store operation after t delay . a store cycle begins only if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver (an internal 100-k ? weak pull-up resistor) that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation, hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by an internal 100-k ? pull-up resistor. sram write operations that are in progress when hsb is driven low by any means are given time (t delay ) to complete before the store operation is initiat ed. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. if the write latch is not set, hsb is not driven low by the device. however, any of the sram read and write cycles are inhibited until hsb is returned high by the host microcontroller or another external source. during any store operation, rega rdless of how it is initiated, the device continues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after the hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power-up) during power-up, or after any low-power condition (v cc preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 9 of 42 preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce or oe controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable autostore is re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce or oe controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual software store operation must be performed to save the autostore state through subs equent power-down cycles. the part comes from the factory with autostore enabled and 0x00 written in all cells. table 2. mode selection ce [8] we oe bhe , ble [9] a 15 - a 0 [10] mode i/o power h x x x x not selected output high z standby l h l l x read sram output data active l l x l x write sram input data active l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active [11] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [11] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [11] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [11] notes 8. tsop ii package is offered in single ce and the bga package is offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). 9. ble , bhe are applicable for the x16 configuration only. 10. while there are 21 address lines on the cy14b116k ( 20 address lines on the cy14b116m), only 13 address lines (a 14 ?a 2 ) are used to control software modes. the remaining address lines are don?t care. 11. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a nonvolatile operation. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 10 of 42 data protection the cy14b116k/cy14b116m protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc is less than v switch. if the cy14b116k/ cy14b116m is in a write mode at power-up (both ce and we are low), after a recall or stor e, the write is inhibited until the sram is enabled after t lzhsb (hsb to output active). this protects against inadvertent writ es during power-up or brown out conditions. real time clock operation nvtime operation the cy14b116k/cy14b116m offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. rtc registers use the last 16 address locations of the sram. internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write oper ation. double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. clock and alarm registers store data in bcd format. rtc functionality is described with respect to cy14b116k in the following sections. the same description applies to cy14b116m, except for the rt c register addresses. the rtc register addresses for cy14b1 16k range from 0x1ffff0 to 0x1fffff, and for cy14b116m,they range from 0xffff0 to 0xfffff. refer to table 6 on page 17 and ta b l e 7 on page 18 for a detailed register map description. clock operations the clock registers maintain time up to 9,999 years in one-second increments. the time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and cent ury transitions. there are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. these registers contain the time of day in the bcd format. bits defined as ?0? are currently not used and are reserved for future use by cypress. reading the clock the double-buffered rtc register structure reduces the chance of reading incorrect data from the clock. internal updates to the cy14b116k time-keeping registers are stopped when the read bit ?r? (in the flags register at 0x1ffff0) is set to ?1? before reading clock data to prevent reading of data in transition. stopping the register updates does not affect clock accuracy. when a read sequence of the rtc device is initiated, the update of the user time-keeping registers stops and does not restart until a ?0? is written to the read bit ?r? (in the flags register at 0x1ffff0). after the end of a read sequence, all the rtc registers are simultaneously updated within 20 ms. setting the clock a write access to the rtc device stops updates to the time keeping registers and enables the time to be set when the write bit ?w? (in the flags register at 0x1ffff0) is set to ?1?. the correct day, date, and time is then writ ten into the registers and must be in the 24-hour bcd format. the time written is referred to as the ?base time?. this value is st ored in nonvolatile registers and used in the calculation of the current time. when the write bit ?w? is cleared by writing ?0? to it , the values of timekeeping registers are transferred to the actual clock counters after which the clock resumes normal operation. if the time written to the time-keeping registers is not in the correct bcd format, each invalid nibble of the rtc registers continues counting to 0xf before rolling over to 0x0, after which rtc resumes normal operation. note after the ?w? bit is set to ?0?, values written into the time-keeping, alarm, calibrati on, and interrupt registers are transferred to the rtc time keeping counters in t rtcp time. these counter values must be saved to nonvolatile memory either by initiating a software/hardware store or autostore operation. while working in the autostore disabled mode, perform a store operation after t rtcp after writing into the rtc registers for the modification s to be correctly recorded. backup power the rtc in the cy14b116k is intended for a permanently powered operation. the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when the primary power, v cc , fails and drops below v switch the device switches to the backup power supply. the clock oscillator uses very little current, which maximizes the backup time available from the backup source. regardless of the clock operation with the primary source removed, the data stored in the nvsram is secure, having been stored in the nonvolatile elements when power was lost. during the backup operation, the cy14b116k consumes 0.45 ? a (typical) at room temperature. choose the capacitor or battery values according to your application. backup time values based on maximum current specifications are shown in the following table. nominal backup times are approximately two times longer. table 3. rtc backup time capacitor value backup time (cy14b116k) 0.1f 2.5 days 0.47f 12 days 1.0f 25 days preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 11 of 42 using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. if a battery is used, a 3-v lithium battery is recommended and the cy14b116k sources current only from the battery when the primary power is removed. however, the battery is not recharged at any time by the cy14b116k. the battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. stopping and starting the oscillator the oscen bit in the calibration register at 0x1ffff8 controls enabling and disabling of the oscillator. this bit is nonvolatile and is shipped to customers in the ? enabled? (set to ?0?) state. to preserve the battery life when the system is in storage, oscen must be set to ?1?. this turns off the oscillator circuit, extending the battery life. if the oscen bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start. while the system power is off, if the voltage on t he backup supply (v rtccap or v rtcbat ) falls below their res pective minimum levels, the oscillator may fail. the cy14b116k can detect oscillator failure when system power is rest ored. this is recorded in the oscillator fail flag (oscf) of th e flags register at the address 0x1ffff0. when the device is powered on (v cc goes above v switch ), the oscen bit is checked for the ?enabled? status. if the oscen bit is enabled and the oscillator is not active within the first 5 ms, the oscf bit is se t to ?1?. the system must check for this condition and then write ?0? to clear the flag. note that in addition to setting the oscf flag bit, the time registers are reset to the ?base time?, which is the value last written to the timekeeping regist ers. the control or calibration registers and the oscen bit are not affected by the ?oscillator failed? condition. the value of oscf must be reset to ?0? when the time registers are written for the first time. this initializes the state of this bit, which may have been set when th e system was first powered on. to reset oscf, set the write bit ?w? (in the flags register at 0x1ffff0) to a ?1? to enable writes to the flags register. write a ?0? to the oscf bit and then reset the write bit to ?0? to disable writes. calibrating the clock the rtc is driven by a quartz-controlled crystal with a nominal frequency of 32.768 khz. the clock accuracy depends on the quality of the crystal and calibration. the crystals available in the market typically have an error of + 20 ppm to + 35 ppm. however, cy14b116k employs a calibration circuit that improves the accuracy to +1/?2 ppm at any given temperature. this implies an error of +2.5 seconds to ?5 seconds per month. the calibration circuit adds or subt racts counts from the oscillator divider circuit to achieve this accuracy. the number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the ca libration register at 0x1ffff8. the calibration bits occupy the five lower order bits in the calibration register. these bits are set to represent any value between ?0? and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibrat ion and a ?0? indicates negative calibration. adding counts speeds the clock up and subtracting counts slows the clock down. if a binary ?1? is loaded into the register, it corresponds to an adju stment of 4.068 or ?2.034-ppm offset in oscillator error, depending on the sign. calibration occurs within a 64-minu te cycle. the first 62 minutes in the cycle may, once every minut e, have one second shortened by 128 or lengthened by 256 oscillator cycles. if a binary ?1? is loaded into the register, only the first two minutes of the 64-minute cycle are modified. if a binary 6 is loaded, the first 12 are affected, and so on. therefor e, each calibration step has the effect of adding 512 or subtractin g 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is, 4.068 or ?2.034 ppm of adjustment for every calibration step in the calibration register. to determine the required calibration, the cal bit in the flags register (0x1ffff0) must be set to ?1?. this causes the int pin to toggle at a nominal frequency of 512 hz. any deviation measured from 512 hz indicates the degree and direction of the required correction. for exam ple, a reading of 512.01024 hz indicates a +20-ppm error. hence, a decimal value of ?10 (001010b) must be loaded into the calibration register to offset this error. note setting or changing the calibration register does not affect the test output frequency. to set or clear cal, set the write bit ?w? (in the flags register at 0x1ffff0) to ?1? to enable writes to the flags register. write a value to cal, and then reset the write bit to ?0? to disable writes. alarm the alarm function compares user-programmed values of alarm time and date (stored in the registers 0x1ffff2-0x1ffff5) with the corresponding time of day and date values. when a match occurs, the alarm interrupt flag (af) is set and an interrupt is generated on the int pin if the alarm interrupt enable (aie) bit is set. there are four alarm match fields ? date, hours, minutes, and seconds. each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field is used in the match process. depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. selecting none of the match bits (all 1s) indicates that no match is required and therefore, the alarm is disabled. selecting all match bits (all 0s) causes an exact time and date match. there are two ways to detect an alarm event: by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x1ffff0 indicates that a date or time match has occurred. the af bit is set to ?1? when a match occurs. reading the flags register clears the alarm flag bit ( and all of the register bits). a hardware interrupt pin may also be used to detect an alarm event. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 12 of 42 to set, clear or enable an alarm, set the ?w? bit (in flags register ? 0x1ffff0) to ?1? to enable writes to alarm registers. after writing the alarm value, clear the ?w? bit back to ?0? for the changes to take effect. note cy14b116k requires the alarm match bit for seconds (bit ?d7? in alarm-seconds register 0x1ffff2) to be set to ?0? for proper operation of alarm flag and interrupt. watchdog timer the watchdog timer is a free-running down counter that uses the 32 hz (31.25 ms period) clock derived from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register 0x1ffff7. note since the watchdog timer uses a free-running 32-hz (31.25 ms period) clock, the start of countdown has a delay between 0 ms and 31.25 ms. the timer consists of a loadable register and a free-running counter. on power-up, the watchdog timeout value in register 0x1ffff7 is loaded in the counter load register, which is shown in figure 6 . counting begins on power-up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to ?1?. the counter is compared to t he terminal value of ?0?. if the counter reaches this value, it causes an internal flag and an optional interrupt output. you c an prevent the timeout interrupt by setting the wds bit to ?1? prior to the counter reaching ?0?. this causes the counter to reload with the watchdog timeout value and to be restarted. if you set the wds bit prior to the counter reaching the terminal value, the interrupt does not occur and the watchdog timer flag is not set. new timeout values are written by setting the watchdog write (wdw) bit to ?0?. when the wdw is ?0?, new writes to the watchdog timeout value bits d5?d0 are enabled to modify the timeout value. when wdw is ?1?, writes to bits d5?d0 are ignored. the wdw function enables you to set the wds bit, without concern that the watchdog timer value is modified. a logical diagram of the watchdog timer is shown in figure 6 . note that setting the watchdog timeout value to ?0? disables the watchdog function. the output of the watchdog timer is the flag bit wdf that is set if the watchdog is allowed to time out. if the watchdog interrupt enable (wie) bit in the interrupt register is set, a hardware interrupt on the int pin is also generated on watchdog timeout. the flag and the hardware interrupt are both cleared when you read the flags register. figure 6. watchdog timer block diagram programmable square wave generator the square wave generator bloc k uses the crystal output to generate a desired frequency on the int pin of the device. the output frequency can be programmed to be one of the following: 1. 1 hz 2. 512 hz 3. 4096 hz 4. 32768 hz the square wave output is not generated while the device is running on backup power. power monitor the cy14b116k provides a power management scheme with power fail interrupt capability. it also controls the internal switch to back up power for the clock and protects the memory from low v cc access. the power monitor is based on an internal bandgap reference circuit that compares the v cc voltage to v switch threshold. when v switch is reached, as v cc decays from power loss, a data store operation is initiated from sram to the nonvolatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source, read and write operations to nvsram are inhi bited and the rtc functions are not available to the user. the rtc clock continues to operate in the background. the updated rtc time keeping registers are available to the user after v cc is restored to the device (see ?autostore/power-up recall characteristics? on page 29). 1 hz oscillator clock divider counter zero compare wdf wds load register wdw d q q watchdog register write to watchdog register 32 hz 32768 hz preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 13 of 42 backup power monitor the cy14b116k provides a backup power monitoring system that detects the backup power (either battery or capacitor backup) failure. the backup power fail flag (bpf) is issued on the next power-up if the backup power fails. the bpf flag is set in the event of backup voltage falling lower than v bakfail . the backup power is monitored even while the rtc is running in the backup mode. low voltage detected during the backup mode is flagged through the bpf flag. bpf can hold the data only until a defined low level of the back up voltage (v dr ). interrupts the cy14b116k has a flags register, interrupt register, and interrupt logic that can signal interrupt to the microcontroller. there are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. each of these can be individually enabled to drive the int pin by appropriate setting in the interrupt register (0x1ffff6). in addition, each has an associated flag bit in the flags register (0x1ffff0) that the host processor uses to determine the cause of the interrupt. the int pin driver has two bits that specify its behavior when an interrupt occurs. an interrupt is raised only if bot h a flag is raised by one of the three sources and the respective interrupt enable bit in the interrupts register is enabled (set to ?1?). after an interrupt source is active, two programmable bits, h/l and p/l, determine the behavior of the output pin driver on the int pin. these two bits are located in the interrupt register and can be used to drive level or pulse mode output from the int pin. in the pulse mode, the pulse width is internally fixed at approximately 200 ms. this mode is intended to reset a host microcontroller. in the level mode, the pin goes to its active polarity until you read the flags register. this mode is used as an interrupt to a host microcontroller. the control bits are summarized in the following section. interrupts are only generated while working on normal power and are not triggered when the system runs in the backup power mode. note cy14b116k generates valid interrupts only after the powerup recall sequence is comp leted. all events on the int pin must be ignored for t hrecall duration after power-up. interrupt register watchdog interrupt enable (wie) . when set to ?1?, the watchdog timer drives the int pin and an internal flag when a watchdog timeout occurs. when wie is set to ?0?, the watchdog timer only affects the wdf flag in flags register. alarm interrupt enable (aie) . when set to ?1?, the alarm match drives the int pin and an internal flag. when aie is set to ?0?, the alarm match only affects the af flag in the flags register. power fail interrupt enable (pfe) . when set to ?1?, the power fail monitor drives the int pin and an internal flag. when pfe is set to ?0?, the power fail monitor only affects the pf flag in the flags register. square wave enable (sqwe) . when set to ?1?, a square wave of programmable frequency is generated on the int pin. the frequency is decided by the sq1 and sq0 bits of the interrupts register. this bit is nonvolatile and survives the power cycle. the sqwe bit overrides all other interrupts. however, the cal bit will take precedence over the squar e wave generator. this bit defaults to ?0? from the factory. high/low (h/l) . when set to ?1?, the int pin is active high and the driver mode is push pull. the int pin drives high only when v cc is greater than v switch . when set to ?0?, the int pin is active low and the drive mode is open drain. the int pin must be pulled up to v cc by a 10-k ? resistor while using the interrupt in active low mode. pulse/level (p/l) . when set to ?1? and an interrupt occurs, the int pin is driven active (determined by h/l) for approximately 200 ms. when p/l is set to ?0?, the int pin is driven high or low (determined by h/l) until the flags or control register is read. sq1 and sq0 . these bits are used together to fix the frequency of the square wave on the int pin output when the sqwe bit is set to ?1?. these bits are nonvolatile and survive the power cycle. the output frequency is decided as illustrated in the following table. while using more than one of the interrupt sources and an interrupt source activates the int pin, the external host must read the flags register to determine the cause of the interrupt. remember that all the flags are cleared when the flags register is read. if the int pin is prog rammed for the level mode, then reading the flag clears the flag and the int pin returns to its inactive state. if the pin is programmed for the pulse mode, then reading the flag clears the flag and the pin. the pulse does not complete its specified duration if t he flags register is read. if the int pin is used as a host reset, then the flags or control register is not read during a reset. setting the calibration bit cal = ?1? or sqwe = ?1? enables square wave output on the int pin. in th is situation, the cal bit setting gets priority over the sqwe bit and enables the 512-hz digital clock output on the int pin for calibration. the cal bit does not survive the power cycle and resets to zero during the next power-up cycle. the setting of sqwe, sq0 and sq1, requires autostore or software store to keep the setting of these bits nonvolatile and enable them to survive the power cycle. when multiple sources are set to drive the interrupt pin (int), then the following priority will be followed to resolve ambiguity as to which cause drives the int pin. table 4. square wave output selection sq1 sq0 frequency comment 0 0 1 hz 1 hz signal 0 1 512 hz 512 hz clock output 1 0 4096 hz 4 khz clock output 1 1 32768 hz oscillator output frequency preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 14 of 42 following is a summary table that shows the state of the int pin, flags register the flags register has three flag bits: wdf, af, and pf, which can be used to generate an interrupt. they are set by the watchdog timeout, alarm match, or power fail monitor respectively. the processor can either poll this register or enable interrupts when a flag is set. th ese flags are automatically reset when the register is read. the flags register is automatically loaded with the value 0x00 on power-up (except for the oscf bit. see stopping and starting the oscillator on page 11 ). table 5. state of the int pin cal sqwe wie/aie/pfe int pin output 1 x x 512 hz 0 1 x square wave output 00 1 alarm 00 0 hi-z figure 7. interrupt block diagram pin driver wie wdf watchdog timer pfe pf aie af clock alarm p/l h/l v cc v ss int sqwe cal mux 512 hz clock square wave priority encoder wie/pie/ aie hi-z control sel line power monitor preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 15 of 42 rtc external components the rtc requires connecting an external 32.768-khz crystal and c 1 , c 2 load capacitance as shown in the figure 8 . the figure shows the recommended rtc external component values. the load capacitances, c 1 and c 2 , are inclusive of parasitic of the printed circuit board (pcb). the pcb parasitic includes the capacitance due to land pattern of crystal pads/pins, x in /x out pads, and copper traces connecting the crystal and device pins. pcb design considerations for rtc the rtc crystal oscillator is a low-current circuit with high-impedance nodes on their crystal pins. due to the low operating current of the rtc circ uit, the crystal connections are very sensitive to noise on the board. hence, it is necessary to isolate the rtc circuit from other signals on the board. it is also critical to minimize the stray capacitance on the pcb. stray capacitances add to the overall crystal load capacitance and, therefore, cause oscill ation frequency errors. proper bypassing and careful layout are required to achieve the optimum rtc performance. layout requirements the board layout must adhere to (but not limited to) the following guidelines during routing rtc circuitry because they help you achieve optimum performance from the rtc design. place the crystal as close as possible to the x in and x out pins. keep the trace lengths between the crystal and rtc equal in length and as short as possible to reduce the probability of noise coupling. keep x in and x out trace width below 8 mils. a wider trace width leads to larger trace capacitance. the larger these bond pads and traces are, the more likely it is that noise can couple from adjacent signals. shield the x in and x out signals by providing a guard ring around the crystal circuitry. this guard ring prevents noise coupling from neighboring signals. take care while routing any other high-speed signal in the vicinity of rtc traces. the more the crystal is isolated from other signals on the board, the less likely it is that noise is coupled into the crystal. maintain a minimum of 200 mil separation between the x in and x out traces, and any other high speed signal on the board. no signals should run underneath crystal components on the same pcb layer. create an isolated solid copper ground plane on the adjacent pcb layer and underneath the crystal circuitry to prevent unwanted noise coupled from trac es routed on the other signal layers of the pcb. the local ground plane should be separated by at least 40 mils from the neighboring plane on the same pcb layer. the solid ground plane should only be in the vicinity of rtc components and its perimeter should be kept equal to the guard ring perimeter. the isolated ground plane should be connected to system ground. figure 9 shows the recom- mended layout for the rtc circuit. figure 8. rtc recommended component configuration [12] note 12. for nonvolatile static random access memory (nvsram) real time clock (rtc) design guidelines and best practices, see applica tion note an61546 . recommended values y 1 = 32.768 khz (12.5 pf) c 1 = 12 pf c 2 = 69 pf note the recommended values for c1 and c2 include board trace capacitance. x out x in y1 c2 c1 preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 16 of 42 figure 9. recommended layout for rtc isolated ground plane on guard ring - top (component) via: via connects to isolated ground plane on l2 via: via connects to system ground plane on l2 c1 c2 y1 layer 2: l2 layer: l1 system ground top component layer: l1 ground plane layer: l2 preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 17 of 42 table 6. rtc register map [13] register bcd format data [14] function/range cy14b116k cy14b116m d7 d6 d5 d4 d3 d2 d1 d0 0x1fffff 0xfffff 10s years years years: 00?99 0x1ffffe 0xffffe 0 0 0 10s months months months: 01?12 0x1ffffd 0xffffd 0 0 10s day of month day of month day of month: 01?31 0x1ffffc 0xffffc 0 0 0 0 0 day of week day of week: 01?07 0x1ffffb 0xffffb 0 0 10s hours hours hours: 00?23 0x1ffffa 0xffffa 0 10s minutes minutes minutes: 00?59 0x1ffff9 0xffff9 0 10s seconds seconds seconds: 00?59 0x1ffff8 0xffff8 oscen (0) 0 cal sign (0) calibration (00000) calibration values [15] 0x1ffff7 0xffff7 wds (0) wdw (0) wdt (000000) watchdog timer 15] 0x1ffff6 0xffff6 wie (0) aie (0) pfe (0) sqwe (0) h/l (1) p/l (0) sq1 (0) sq0 (0) interrupts [15] 0x1ffff5 0xffff5 m (1) 0 10s alarm day of month alarm, day of month alarm, day of month: 01?31 0x1ffff4 0xffff4 m (1) 0 10s alarm hours alarm, hours alarm, hours: 00?23 0x1ffff3 0xffff3 m (1) 10s alarm minutes alarm, minutes alarm, minutes: 00?59 0x1ffff2 0xffff2 m (1) 10s alarm seconds alarm, seconds alarm, seconds: 00?59 0x1ffff1 0xffff1 10s centuries centuries centuries: 00?99 0x1ffff0 0xffff0 wdf af pf oscf [16] bpf [16] cal (0) w (0) r (0) flags [15] notes 13. upper byte d 15 -d 8 (cy14b116m) of rtc registers are reserved for future use. 14. ( ) designates values shipped from the factory. 15. this is a binary value, not a bcd value. 16. when you reset oscf and bpf flag bits, the flags register will be updated after t rtcp time. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 18 of 42 table 7. register map detail register description cy14b116k cy14b116m 0x1fffff 0xfffff time keeping - years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0?99. 0x1ffffe 0xffffe time keeping - months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. the range for the register is 1?12. 0x1ffffd 0xffffd time keeping - day of month d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. the range for the register is 1?31. le ap years are automatically adjusted for. 0x1ffffc 0xffffc time keeping - day of week d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble (three bits) contains a value that corre lates to the of the week. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, because the day is not integrated with the date. 0x1ffffb 0xffffb time keeping - hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s hours hours contains the bcd value of hours in 24 hour fo rmat. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0?23. 0x1ffffa 0xffffa time keeping - minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. the range for the register is 0?59. 0x1ffff9 0xffff9 time keeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains th e upper digit and operates from 0 to 5. the range for the register is 0?59. 0x1ffff8 0xffff8 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 19 of 42 oscen 0 calibration sign calibration oscen oscillator enable. when set to ?1?, the oscillator is stopped. when set to ?0?, the oscillator runs. disabling the oscillator saves battery or capacitor power during storage. calibration sign determines if the calibration adju stment is applied as an addition (1) to or as a subtraction (0) from the time-base. calibration these five bits control the calibration of the clock. 0x1ffff7 0xffff7 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to ?1? reloads and restarts the watchdog timer. setting the bit to ?0? has no effect. the bit is cleared automatically after the watchdog timer is reset. the wds bit is write only. reading it always returns a 0. wdw watchdog write enable. setting this bit to ?1? disables any write to the watchdog timeout value (d5?d0). this allows you to set the watchdog st robe bit without disturbing the timeout value. setting this bit to ?0? allows bits d5?d0 to be wr itten to the watchdog register when the next write cycle is complete. this function is explained in more detail in watchdog timer on page 12 . wdt watchdog timeout selection. the watchdog timer interval is selected by the 6-bit value in this register. it represents a multipli er of the 32-hz count (31.25 ms). the range of timeout value is 31.25 ms (a setting of 01h) to 2 seconds (setting of 3fh). setting the watchdog timer register to 0 disables the timer. these bits can be written only if the wdw bit was set to ?0? on a previous cycle. note since the watchdog timer uses a free-running 32-hz (31.25 ms period) clock, the set time interval has an additional time between 0 ms and 31.25 ms. 0x1ffff6 0xffff6 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfe sqwe h/l p/l sq1 sq0 wie watchdog interrupt enable. when set to ?1? an d a watchdog timeout occurs, the watchdog timer drives the int pin and the wdf flag. when set to ?0?, the watchdog timeout affects only the wdf flag. aie alarm interrupt enable. when set to ?1?, the al arm match drives the int pin and the af flag. when set to ?0?, the alarm matc h only affects the af flag. pfe power fail enable. when set to ?1?, the power fail monitor drives the int pin and the pf flag. when set to ?0?, the power fail moni tor affects only the pf flag. sqwe square wave enable. when set to ?1?, a square wave is driven on the int pin with frequency programmed using sq1 and sq0 bits. the square wa ve output takes precedence over interrupt logic. if the sqwe bit is set to ?1?. when an enabled interrupt source becomes active, only the corresponding flag is raised and the int pin continues to drive the square wave. h/l high/low. when set to 1, the int pin is driven active high. when set to 0, the int pin is open drain, active low. p/l pulse/level. when set to ?1?, the int pin is driven active (determined by h/l) by an interrupt source for approximately 200 ms. when set to ?0?, the int pi n is driven to an active level (as set by h/l) until the flags register is read. sq1, sq0 sq1, sq0. these bits are used to decide the frequency of the square wave on the int pin output when sqwe bit is set to ?1?. the following is th e frequency output for each combination of sq1, sq0: (0, 0) - 1 hz (0, 1) - 512 hz (1, 0) - 4096 hz (1, 1) - 32768 hz table 7. register map detail (continued) register description cy14b116k cy14b116m preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 20 of 42 0x1ffff5 0xffff5 alarm - day of month d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm day of month alarm day of month contains the alarm value for the date of the month and t he match bit to select or deselect the date value. m match. when this bit is set to ?0?, the date value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the date value. 0x1ffff4 0xffff4 alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the match bit to select or deselect the hours value. m match. when this bit is set to ?0?, the hours value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the hours value. 0x1ffff3 0xffff3 alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm minutes alarm minutes contains the alarm value for the minutes and the match bit to select or deselect the minutes value. m match. when this bit is set to ?0?, the minutes val ue is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the minutes value. 0x1ffff2 0xffff2 alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm seconds alarm seconds contains the alarm value for the seconds and the match bit to select or deselect the second?s value. m match. when this bit is set to ?0?, the seconds valu e is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the seconds value. 0x1ffff1 0xffff1 time keeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 10s centuries centuries contains the bcd value of centuries. lower nibbl e contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and op erates from 0 to 9. the range for the register is 0-99 centuries. table 7. register map detail (continued) register description cy14b116k cy14b116m preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 21 of 42 0x1ffff0 0xffff0 flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf bpf cal w r wdf watchdog timer flag. this read-only bit is set to ?1? when the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags register is read or on power-up af alarm flag. this read-only bit is set to ?1? when the time and date match the values stored in the alarm registers with the match bits = 0. it is cleared when the flags register is read or on power-up. pf power fail flag. this read-only bit is set to ?1? when power falls below the power fail threshold v switch . it is cleared when the flags register is read. oscf oscillator fail flag. set to ?1? on power-up if the oscillator is enabled and not running in the first 5 ms of operation. this indicates that rtc backup power failed and clock value is no longer valid. this bit survives the power cycle and is never clea red internally by the chip. the user must check for this condition and write 0 to clear this flag . when user resets oscf flag bit, the bit will be updated after t rtcp time. bpf backup power fail flag. set to ?1 ? on power-up if the backup power (battery or capacitor) failed. the backup power fail condition is determined by the voltage falling below their respective minimum specified voltage. bpf can hold the data only till a defined low level of the back up voltage (v dr ). user must reset this bit to clear this fl ag. when user resets bpf flag bit, the bit will be updated after t rtcp time. cal calibration mode. when set to ?1?, a 512-hz sq uare wave is output on the int pin. when set to ?0?, the int pin resumes normal operation. th is bit takes priority over sq0/sq1 and other functions. this bit defaults to 0 (disabled) on power-up. w write enable: setting the ?w? bit to ?1? freezes updat es of the rtc registers. you can then write to rtc registers, alarm registers, ca libration register, interrupt regist er and flags register. setting the ?w? bit to ?0? causes the contents of the rtc regi sters to be transferred to the time keeping counters if the time has changed. this transfer process takes t rtcp time to complete. this bit defaults to 0 on power-up. r read enable: setting ?r? bit to ?1?, stops clock upd ates to user rtc registers so that clock updates are not seen during the reading process. set ?r? bit to ?0? to resume clock updates to the holding register. setting this bit does not require ?w? bit to be set to ?1?. this bit defaults to 0 on power-up. table 7. register map detail (continued) register description cy14b116k cy14b116m preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 22 of 42 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c maximum accumulated storage time at 150 ? c ambient temperature .................................. 1000 h at 85 ? c ambient temperature.................... ............. 20 years maximum junction temperature .................................. 150 ? c supply voltage on v cc relative to v ss .........?0.5 v to +4.1 v voltage applied to outputs in high-z state...................................... ?0.5 v to v cc + 0.5 v input voltage .........................................?0.5 v to vcc + 0.5 v transient voltage (<20 ns) on any pin to ground potential . ............ ..... ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. .1.0 w surface mount lead soldering temperature (3 seconds) ......... .............. .............. ..... +260 ? c dc output current (1 output at a time, 1s duration) ..... 20 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch-up current .................................................... > 140 ma operating range product range ambient temperature (t a ) v cc cy14b116k/ cy14b116m industrial ?40 ? c to +85 ? c 2.7 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [17] max unit v cc power supply 2.7 3.0 3.6 v i cc1 average v cc current values obtained without output loads (i out = 0 ma) t rc = 25 ns ? ? 95 ma t rc = 45 ns ? ? 75 ma icc2 average v cc current during store all inputs don?t care, v cc = v cc (max). average current for duration t store ??10ma i cc3 average v cc current at t rc = 200 ns, v cc (typ), 25 c all inputs cycling at cmos levels. values obtained without output loads (i out = 0 ma). ?50 ?ma i cc4 [18] average v cap current during autostore cycle all inputs don?t care. average current for duration t store ?? 6ma i sb v cc standby current ce > (v cc ? 0.2 v). v in < 0.2 v or > (v cc ? 0.2 v). ?w? and ?r? bit set to ?0?. standby current level after non volatile cycle is complete. inputs are static. f = 0 mhz. t rc = 25 ns ? ? 750 ? a t rc = 45 ns ? ? 600 ? a i zz sleep mode current all inputs are static at cmos level; rtc running on backup power supply. ??10 ? a i ix [19] input leakage current (except hsb ) v cc = v cc (max), v ss < v in < v cc ?1 ? +1 ? a input leakage current (for hsb ) v cc = v cc (max), v ss < v in < v cc ?100 ? +1 ? a i oz off state output leakage current v cc = v cc (max), v ss < v out < v cc , ce or oe > v ih or ble /bhe > v ih or we < v il ?1 ? +1 ? a notes 17. typical values are at 25 c, v cc = v cc (typ). not 100% tested. 18. this parameter is only guaranteed by design and is not tested. 19. the hsb pin has i out = -2 ua for v oh of 2.4 v when both active high and low driver s are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 23 of 42 v ih input high voltage 2.0 ? v cc + 0.5 v v il input low voltage v ss ? 0.5 ? 0.8 v v oh output high voltage i out = ?2 ma 2.4 ? ? v v ol output low voltage i out = 4 ma ? ? 0.4 v v cap [20] storage capacitor between v cap pin and v ss 19.8 22.0 82.0 ? f v vcap [21, 22] maximum voltage driven on v cap pin by the device v cc = v cc (max) ? ? 5.0 v data retention and endurance over the operating range parameter description min unit data r data retention 20 years nv c nonvolatile store operations 1,000,000 cycles capacitance in the following table, the capacitance parameters are listed. [22] parameter description test conditions max (all packages except 165-fbga) max (165-fbga package) unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = v cc (typ) 810pf c io input/output capacitance 8 10 pf c out output capacitance 8 10 pf thermal resistance in the following table, the thermal resistance parameters are listed. [22] parameter description test conditions 44-tsop ii 54-tsop ii 165-fbga unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 44.6 41.1 15.6 ? c/w ? jc thermal resistance (junction to case) 2.4 4.6 2.9 ? c/w dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [17] max unit notes 20. min v cap value guarantees that there is a sufficient charge available to complete a successful autostore operation. max v cap value guarantees that the capacitor on v cap is charged to a minimum voltag e during a power-up recall cycle so that an immediate power-down cycle can complete a successful autostore. therefore, it is always recommended to use a capacitor within the specified min and max limits. 21. maximum voltage on v cap pin (v vcap ) is provided for guid ance when choosing the v cap capacitor. the voltage rating of the v cap capacitor across the operating temperature range should be higher than the v vcap voltage 22. these parameters are only guaranteed by design and are not tested. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 24 of 42 ac test conditions input pulse levels....................................................0 v to 3 v input rise and fall times (10% - 90%)........................... < 3 ns input and output timing reference levels........................ 1.5 v figure 10. ac test loads and waveforms 3.0 v output c l r1 r2 789 ? 3.0 v output c l r1 r2 789 ? 577 ? 577 ? for tristate specs 5 pf 30 pf rtc characteristics over the operating range parameters description min typ [23] max units v rtcbat rtc battery pin voltage 1.8 3.0 3.6 v i bak [24] rtc backup current t a = ?40 ? c? ? 0.45 ? a t a = 25 c?0.45? ? a t a = 85 c ? ? 0.60 ? a v rtccap [25] rtc capacitor pin voltage t a = ?40 ? c1.6?3.6v t a = 25 c 1.5 3.0 3.6 v t a = 85 c1.4?3.6v v bakfail backup failure threshold 1.8 ? 2.2 v v dr bpf flag retention voltage 1.6 ? - v tocs rtc oscillator time to start ? 1 2 sec t rtcp rtc processing time from end of ?w? bit set to ?0? ? ? 1 ms r bkchg rtc backup capacitor charge current-limiting resistor 350 ? 850 ? notes 23. typical values are at 25 c, v cc = v cc (typ). not 100% tested. 24. from either v rtccap or v rtcbat. 25. if v rtccap > 0.5 v or if no capac itor is connected to v rtccap pin, the oscillator starts in tocs time. if a backup capacitor is connected and v rtccap < 0.5 v, the capacitor must be allowed to charge to 0.5 v for oscillator to start. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 25 of 42 ac switching characteristics over the operating range [26] parameters description 25 ns 45 ns unit cypress parameter alt parameter min max min max sram read cycle t ace t acs chip enable access time ? 25 ? 45 ns t rc [27] t rc read cycle time 25 ? 45 - ns t aa [28] t aa address access time ? 25 ? 45 ns t doe t oe output enable to data valid ? 12 ? 20 ns t oha [28] t oh output hold after address change 3 ? 3 ? ns t lzce [29] t lz chip enable to output active 3 ? 3 ? ns t hzce [ 29, 30] t hz chip disable to output inactive ? 10 ? 15 ns t lzoe [29] t olz output enable to output active 0 ? 0 ? ns t hzoe [29, 30] t ohz output disable to output inactive ? 10 ? 15 ns t pu [29] t pa chip enable to power active 0 ? 0 ? ns t pd [29] t ps chip disable to power standby ? 25 ? 45 ns t dbe byte enable to data valid ? 12 ? 20 ns t lzbe [29] byte enable to output active 0 ? 0 ? ns t hzbe [29, 30] byte disable to output inactive ? 10 ? 15 ns sram write cycle t wc t wc write cycle time 25 ? 45 ? ns t pwe t wp write pulse width 20 ? 30 ? ns t sce t cw chip enable to end of write 20 ? 30 ? ns t sd t dw data setup to end of write 10 ? 15 ? ns t hd t dh data hold after end of write 0 ? 0 ? ns t aw t aw address setup to end of write 20 ? 30 ? ns t sa t as address setup to start of write 0 ? 0 ? ns t ha t wr address hold after end of write 0 ? 0 ? ns t hzwe [29, 30, 31] t wz write enable to output disable ? 10 ? 15 ns t lzwe [29] t ow output active after end of write 3 ? 3 ? ns t bw byte enable to end of write 20 ? 30 ? ns notes 26. test conditions assume a signal transition time of 3 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc (typ), and output loading of the specified i ol /i oh and 30 pf load capacitance as shown in figure 10 on page 24. 27. we must be high during sram read cycles. 28. device is continuously selected with ce , oe and ble , bhe low. 29. these parameters are only guaranteed by design and are not tested. 30. t hzce , t hzoe , t hzbe and t hzwe are specified with a load capacitance of 5 pf. transition is measured 200 mv from the steady state output voltage. 31. if we is low when ce goes low, the outputs remain in the high impedance state. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 26 of 42 figure 11. sram read cycle 1: address controlled [32, 33, 34] figure 12. sram read cycle 2: ce and oe controlled [32, 34, 35] address data output address valid previous data valid output data valid t rc t aa t oha address valid address data output output data valid standby active high impedance ce oe bhe, ble i cc t hzce t rc t ace t aa t lzce t doe t lzoe t dbe t lzbe t pu t pd t hzbe t hzoe [36] notes 32. we must be high during sram read cycles. 33. device is continuously selected with ce , oe and ble , bhe low. 34. hsb must remain high duri ng read and write cycles. 35. ble , bhe are applicable for x16 configuration only. 36. tsop ii package is offered in single ce and bga package is offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 27 of 42 figure 13. sram write cycle 1: we controlled [37, 38, 39, 40] figure 14. ram write cycle 2: ce controlled [37, 38, 39, 40] data output data input input data valid high impedance address valid address previous data t wc t sce t ha t bw t aw t pwe t sa t sd t hd t hzwe t lzwe we bhe, ble ce [41] notes 37. ble , bhe are applicable for x16 configuration only. 38. if we is low when ce goes low, the outputs remain in the high impedance state. 39. hsb must remain high during read and write cycles. 40. ce or we must be > v ih during address transitions. 41. tsop ii package is offered in single ce and bga package is offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sa t sce t ha t bw t pwe [41] preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 28 of 42 figure 15. sram write cycle 2: ce controlled [42, 43, 44, 45] figure 16. sram write cycle 3: bhe , ble controlled [42, 43, 44, 45, 47] notes 42. ble , bhe are applicable for x16 configuration only. 43. if we is low when ce goes low, the outputs remain in the high impedance state. 44. hsb must remain high during read and write cycles. 45. ce or we must be > v ih during address transitions. 46. tsop ii package is offered in single ce and bga package is offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). 47. only ce and we controlled writes to rtc registers are allowed. ble pin must be held low before ce or we pin goes low for writes to rtc register. data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sa t sce t ha t bw t pwe [46] (not applicable for rtc register writes) data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sce t sa t bw t ha t aw t pwe [46] preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 29 of 42 autostore/power-up recall characteristics over the operating range parameter description cy14b116k/cy14b116m unit min max t hrecall [48] power-up recall duration ? 30 ms t store [49] store cycle duration ? 8 ms t delay [50, 51] time allowed to comple te sram write cycle ? 25 ns v switch low voltage trigger level ? 2.65 v t vccrise [51] v cc rise time 150 ? ? s v hdis [51] hsb output disable voltage ? 1.9 v t lzhsb [51] hsb to output active time ? 5 ? s t hhhd [51] hsb high active time ? 500 ns figure 17. autostor e or power-up recall [52] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power-up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power -down autostore note note note note v cc [49] [49] [53] [53] notes 48. t hrecall starts from the time v cc rises above v switch. 49. if an sram write has not taken place since the last nonvolatile cycle, no au tostore or hardware store takes place. 50. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 51. these parameters are only guaranteed by design and are not tested. 52. read and wr ite cycles are ignored during store, recall, and while v cc is below v switch. 53. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 30 of 42 sleep mode characteristics over the operating range parameter description cy14b116k/cy14b116m unit min max t wake sleep mode exit time (zz high to first access after wakeup) ? 30 ms t sleep sleep mode enter time (zz low to ce don?t care) ? 8 ms t zzl zz active low time 50 ? ns t wezz last write to sleep mode entry time 0 ? ? s t zzh zz active to dq hi-z time ? 70 ns figure 18. sleep mode [54] wake t v zz we data dq t sleep t zzh t hrecall v switch v switch cc read & write inhibited (rwi) power-up recall read & write power -down autostore sleep entry t wezz sleep sleep exit read & write note 54. device initiates sleep routine and enters into sleep mode after t sleep duration. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 31 of 42 software controlled store and recall characteristics over the operating range [55, 56] parameter description 25 ns 45 ns unit min max min max t rc store/recall initiation cycle time 25 ? 45 ? ns t sa address setup time 0 ? 0 ? ns t cw clock pulse width 20 ? 30 ? ns t ha address hold time 0 ? 0 ? ns t recall recall duration ? 600 ? 600 ? s t ss [57, 58] soft sequence processing time ? 500 ? 500 ? s figure 19. ce and oe controlled software store and recall cycle [56] figure 20. autostore enable and disable cycle t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb (store only) dq (data) rwi t delay note [59] [60] t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss note rwi [59] [60] notes 55. the software sequence is clocked with ce controlled or oe controlled reads. 56. the six consecutive addresses must be read in the order listed in ta b l e 2 . we must be high during all six consecutive cycles. 57. this is the amount of time it takes to take action on a soft sequence command. v cc power must remain high to effectively register command. 58. commands such as store and recall lock out i/o until operation is complete which further increases this time. see the specif ic command. 59. tsop ii package is offered in single ce and bga package is offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). 60. dq output data at the sixth read may be invalid since the output is disabled at t delay time. preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 32 of 42 hardware store characteristics over the operating range parameter description cy14b116k/cy14b116m unit min max t dhsb hsb to output active time when write latch not set ? 25 ns t phsb hardware store pulse width 15 ? ns figure 21. hardware store cycle [61] figure 22. soft sequence processing [62, 63] ~ ~ hsb (in) hsb (out) rwi hsb (in) hsb (out) rwi t hhhd t store t phsb t delay t lzhsb t delay t phsb hsb pin is driven high to v cc only by internal 100 k : resistor, hsb driver is disabled sram is disabled as long as hsb (in) is driven low. write latch not set write latch set address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw [64] notes 61. if an sram write has not taken place since the last nonvol atile cycle, no autostore or hardware store takes place. 62. this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively reg ister a command. 63. commands such as store and recall lock out i/o until the operat ion is complete, which further increases this time. see the s pecific command. 64. the tsop ii package is offered in single ce and bga package is offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 33 of 42 truth table for sram operations hsb should remain high for sram operations. for 8 configuration single chip enable option (44-pin tsop ii package) ce we oe inputs and outputs mode power h x x high-z deselect/power-down standby l h l data out (dq 0 ?dq 7 ); read active l h h high-z output disabled active llxdata in (dq 0 ?dq 7 ); write active for 16 configuration single chip enable option (54-pin tsop ii package) ce we oe ble bhe inputs and outputs mode power hxxxxhigh-z deselect/power-downstandby l x x h h high-z output disabled active lhllldata out (dq 0 ?dq 15 ) read active l h l l h data out (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z read active lhlhldata out (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z read active l h h x x high-z output disabled active l l x l l data in (dq 0 ?dq 15 ) write active l l x l h data in (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z write active l l x h l data in (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z write active preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 34 of 42 for 16 configuration dual chip enable option (165-ball fbga package) ce 1 ce 2 we oe ble bhe inputs and outputs mode power h x x x x x high-z deselect/power-down standby x l x x x x high-z deselect/power-down standby l h x x h h high-z output disabled active l h h l l l data out (dq 0 ?dq 15 ) read active lhhllhdata out (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z read active l h h l h l data out (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z read active l h h h x x high-z output disabled active l h l x l l data in (dq 0 ?dq 15 ) write active lhlxlhdata in (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z write active l h l x h l data in (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z write active preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 35 of 42 ordering code definition ordering information speed (ns) ordering code package diagram package type operating range 25 cy14b116k-zs25xi 51-85087 44-pin tsop ii industrial cy14b116k-zs25xit 51-85087 44-pin tsop ii CY14B116M-ZSP25XI 51-85160 54-pin tsop ii 45 cy14b116k-zs45xi 51-85087 44-pin tsop ii cy14b116k-zs45xit 51-85087 44-pin tsop ii cy14b116m-bz45xi 51-85195 165-ball fbga all parts are pb-free. contact your local cypress sales representative for availability of these parts. option: t - tape & reel blank - std. speed: 25 - 25 ns data bus: k - 8 + rtc m - 16 + rtc density: 116 - 16-mbit voltage: b - 3.0 v cypress cy14 b 116 k - zs 25 x i t nvsram 14 - temperature: i - industrial (?40 to 85 c) pb-free package: zs p- 44-tsop ii 45 - 45 ns zsp - 54-tsop ii bza - 165-fbga preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 36 of 42 package diagrams figure 23. 44-pin tsop ii package outline (51-85087) 51-85087 *e preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 37 of 42 figure 24. 54-pin tsop ii package outline (51-85160) package diagrams (continued) 51-85160 *e preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 38 of 42 figure 25. 165-ball fbga (15 mm 17 mm 1.40 mm) package outline (51-85195) package diagrams (continued) 51-85195 *c preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 39 of 42 acronyms document conventions units of measure all errata for this product are fixed, effective date code 1431 (yy=14, ww=31). for more informat ion, refer to datasheet 001-67 786 rev. *g or contact cypress technical support at http://www.cypre ss.com/support . acronym description bcd binary coded decimal cmos complementary metal oxide semiconductor eia electronic industries alliance fbga fine-pitch ball grid array i/o input/output jesd jedec standards nvsram nonvolatile static random access memory rohs restriction of hazardous substances rtc real time clock rwi read and write inhibited tsop ii thin small outline package symbol unit of measure c degree celsius hz hertz kbit kilobit khz kilohertz k ? kilohm ? a microampere ma milliampere ? f microfarad mbit megabit mhz megahertz ? s microsecond ms millisecond ns nanosecond ? ohm pf picofarad v volt w watt preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 40 of 42 document history page document title: cy14b116k/cy14b116m, 16-mbit (2048 k 8/1024 k 16) nvsram with real time clock document number: 001-67786 rev. ecn no. orig. of change submission date description of change ** 3188189 gvch 03/04/2011 new datasheet *a 3457528 gvch 12/13/2011 datasheet status changed from ?advance? to ?preliminary? pin diagrams: updated figure 3 and figure 3 table 1 : updated zz pin description added footnote 7 and 13 i cc1 parameter spec value changed from 70 ma to 95 ma and 50 ma to 75 ma for 25 ns and 45 ns access speed respectively. i cc3 parameter spec value changed from 35 ma to 50 ma i cc4 parameter spec value changed from 10 ma to 6 ma i sb parameter spec value changed from 500 ua to 750 ua added v cap value for cy14c116x changed v cap typ value from 27 uf to 22 uf added thermal resistance values added footnote 20 and 32 rtc characteristics : updated i bak and v rtccap parameter spec values changed t hrecall parameter spec value from 40 ms to 60 ms for cy14c116x and from 20 ms to 30 ms for cy14b116x/cy14e116x. changed t wake parameter spec value from 40 ms to 60 ms for cy14c116x and from 20 ms to 30 ms for cy14b116x/cy14e116x. t recall spec value changed from 300 us to 600 us t ss spec value changed from 200 us to 500 us updated ordering information package diagrams : updated 165-fbga package diagram *b 3514357 zsk 02/07/2012 no technical updates. *c 3944873 gvch 03/26/2013 removed 2.5 v and 5 v operating range voltage support removed 32 configuration support added 54 - pin tsop ii package added figure 5 ( sleep mode (zz) flow diagram ) updated real time clock operation description updated maximum ratings (changed ?ambient temperature with power applied? to ?maximum junction temperature?). changed c in and c out value from 7 pf to 8 pf changed v ih max spec value from v cc + 0.3 v to v cc + 0.5 v added v vcap parameter spec added footnote 21 changed v bakfail spec max value from 2.0 v to 2.2 v changed t rtcp max value from 350 s to 1 ms. updated t zzl parameter spec value from 15 ns to 50 ns added figure 18 added footnote 54 preliminary cy14b116k/cy14b116m document #: 001-67786 rev. *i page 41 of 42 *d 4260504 gvch 01/24/2014 modified logic block diagram for more clarity. updated autostore operation (power-down) : removed sentence ?the hsb signal is monitored by the system to detect if an autostore cycle is in progress.? modified figure 5 for more clarity. added note in watchdog timer and table 7 (watchdog timer section) to clarify additional delay at the start of countdown. added pcb design considerations for rtc added i sb max spec value for 45 ns access speed changed v cap min spec value from 20 ? f to 19.8 ? f added thermal resistance values for 54-tsop ii package added footnote 30 updated figure 18 for more clarity changed t zzh max spec value from 20 ns to 70 ns. *e 4366689 gvch 05/01/2014 updated sleep mode : updated description. updated thermal resistance values added note 17 and 30. added . updated in new template. *f 4417851 gvch 06/24/2014 dc electrical characteristics : added r bit set to ?0? to i sb test condition added footnote 18 updated maximum value of v vcap parameter from 4.5 v to 5.0 v capacitance : updated c in and c out value from 8 pf to 10 pf for 165-fbga package added c io parameter. *g 4432183 gvch 07/07/2014 dc electrical characteristics : updated maximum value of v cap parameter from 120.0 ? f to 82.0 ? f *h 4456803 zsk 07/31/2014 removed errata section. added a note at the end of the document mentioning when the errata items were fixed. *i 4562106 gvch 11/05/2014 added related documentation hyperlink in page 1. updated package diagram 51-85160 to current revision document history page (continued) document title: cy14b116k/cy14b116m, 16-mbit (2048 k 8/1024 k 16) nvsram with real time clock document number: 001-67786 rev. ecn no. orig. of change submission date description of change document #: 001-67786 rev. *i revised november 5, 2014 page 42 of 42 all products and company names mentioned in this document are the trademarks of their respective holders. preliminary cy14b116k/cy14b116m ? cypress semiconductor corporation, 2011-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc 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